A field-programmable gate array is a programmable device typically having a logic core surrounded by a ring of input/output (I/O) buffers. As silicon technology migrates to smaller and smaller devices and as core logic densities increase, the ratio of core logic to I/O buffers increases. In general, however, the physical size of I/O buffers has not been shrinking as fast as the physical size of the core logic. One solution to this phenomenon has been to implement narrow, elongated I/O buffers around the periphery of newer devices. Unfortunately, this approach significantly increases the cost of the devices.
Another factor contributing to the relatively large size of I/O buffers is the trend towards providing I/O circuitry with multiple different types of buffers connected to individual pads, for example, in order to support multiple different signaling applications. Unfortunately, this increased amount of circuitry results in increased levels of capacitance as seen from the pads, which increased capacitance adversely affects the higher-performance signaling applications.